In typical circuit design, circuit components are arranged to optimize space and/or circuit performance. Such arrangements can include the “layout” or pattern definition of each of the layers used in a semiconductor manufacturing process. For example, such layout can include metal interconnect or connectivity layers that are converted to masks or reticles for use in a wafer fabrication facility that manufactures ICs (i.e., “chips”).
While some circuits are designed using “custom” layout, others are designed using a partially or fully automated design flow. Application-Specific Integrated Circuit (ASIC) designs, as well as other functional blocks within a larger chip, such as System-On-Chip (SOC) designs, may employ custom and/or ASIC type flows on the same chip. In any event, typical ASIC flows use “place-and-route” tools for placing logic or circuit “blocks” and then “routing” or connecting the interface signals between the blocks. Such routing between circuit blocks is typically done using one or more metal connectivity layers.
Referring now to FIG. 1, a box diagram showing a conventional routing for a high fanout signal path is indicated by the general reference character 100. Logic Block 102 is connected to Logic Blocks 104, 106, 108, and 110 via signal path 112. Such a multiple load and/or connection signal path may be considered a “high fanout” signal path for automated routing purposes. As shown, timing delays due to unmatched signal path routing can result in a delay D1 between Logic Blocks 104 and 106, a delay D1+D2 between Logic Blocks 104 and 108, and a delay D1+D2+D3 between Logic Blocks 104 and 110. Among the conventional approaches to address this timing disparity are: (i) the insertion of buffer stages; (ii) custom-routing high fanout signals; and/or (iii) adjusting block placements in order to obtain more favorable signal routing.
However, such conventional approaches to high fanout signal path routing are not desirable in an automated place-and-route flow. Inserting extra buffer stages merely for signal path routing facilitation takes chip layout area away from other functional circuit blocks and may increase a signal delay. Custom-routing high fanout signals can be a time consuming process that essentially defeats at least part of the purpose of an automated place-and-route flow. Similarly, adjusting block placements in order to assist high fanout signal routing may also be a time consuming process that does not effectively comport with an automated flow. Accordingly, signal path routing using conventional approaches may not improve high fanout signal path timing characteristics in an efficient manner.
Given the increasing demands on circuit designers to create chips of increasing density, decreasing wire and transistor widths, and decreasing power supply and power consumption, it is difficult to ensure optimal high fanout signal path timing in an automated place-and-route flow. Increasing the complexity, flexibility and/or functionality of the circuitry on a chip exacerbates these challenges. Thus, what is needed is a tool with which integrated circuit designers can efficiently optimize high fanout signal path routing and/or timing in an automated place-and-route flow.